1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a clock generation circuit of a semiconductor apparatus.
2. Related Art
In general, a semiconductor apparatus including a memory performs an operation in synchronization with a clock. Accordingly, in a synchronous type semiconductor apparatus, input data and output data should be precisely synchronized with an external clock. The semiconductor apparatus receives the external clock, converts the external clock into an internal clock, and uses the converted internal clock. However, as the internal clock is transmitted through a clock buffer and a transmission line, a phase difference occurs between the internal clock and the external clock. Therefore, in order to compensate for the phase difference, the semiconductor apparatus generally includes a phase-locked loop or a delay-locked loop.
The delay-locked loop may increase an effective data output period by compensating for the phase difference occurring between the internal clock and the external clock. The delay-locked loop causes the phase of the internal clock to precede the phase of the external clock by a predetermined time, such that output data can be outputted by being synchronized with the external clock.
FIG. 1 is a block diagram schematically showing the configuration of a conventional delay-locked loop 10. In FIG. 1, the delay-locked loop 10 includes a delay line 11, a delay modeling block 12, a phase detection block 13, an update signal generation block 14, a delay line control block 15, and a clock driver 16. The delay line 11 receives an input clock CLKI and generates a delayed clock CLKD. The delay line 11 delays the input clock CLKI by the value set by the delay line control block 15. The delay modeling block 12 delays the delayed clock CLKD by a modeled delay value and generates a feedback clock CLKF. The phase detection block 13 compares the phases of the input clock CLKI and the feedback clock CLKF and generates a detection signal DET. The update signal generation block 14 receives the detection signal DET and generates an update signal VALID. The delay line control block 15 receives the update signal VALID and may update the delay value of the delay line 11. The clock driver 16 receives the delayed clock CLKD and generates first and second output clocks RCLK_DLL and FCLK_DLL.
In the case where the phase difference between the input clock CLKI and the feedback clock CLKF is large, the delay-locked loop 10 should update the delay value of the delay line 11 by being operated a multitude of times, and thus, a delay locking operation time for generating the output clocks RCLK_DLL and FCLK_DLL is lengthened.